This application makes reference to, incorporates the same herein, and claims all benefits accruing under 35 U.S.C. Section 119 from an application for DATA PACKET RE-SEQUENCER filed earlier in the Korean Industrial Property Office on Dec. 28, 1998 and there duly assigned Ser. No. 59200/1998.
1. Field of the Invention
The present invention relates to an ATM (Asynchronous Transfer Mode) switching system, and more particularly a data re-sequencer used in an ATM switching system to re-sequence data packets.
2. Description of the Related Art
ATM is a high-speed digital communications process for use in ISDN applications which attempts to address many of the problems associated with the transmission and reception of several different types of information. For example, file transfer is most efficiently accomplished through connectionless communications with large packets, whereas real-time voice and video communication work best with a connection-oriented scheme and small packets. ATM has been designed to handle both of these types of information. The term xe2x80x9cdata packetxe2x80x9d is hereinafter referred to as xe2x80x9cdata cell,xe2x80x9d which is a short fixed-length section of data transmitted as a unit in ATM. For example, the ATM switching system divides the transmitted information into a number of data cells, each of which may consist of 48 bytes including a 5-byte header.
Meanwhile, the ATM switching system switches the data cells coming into the input port through a single path or multiple paths. In the case of the single path, the switching system must be designed to have a much faster internal data processing speed than the speed of the cell coming into the input port in order to deal with the burst traffic. The multi-path switching system is developed to effectively deal with the speed problem of the single path switching system, which requires a multi-path and multi-stage switching network to have large capacity. However, the multi-path switching system may suffer undesirable transmission delay of the data cells because they are switched through the internal multiple paths to the output port. This requires re-sequencing of the data cells outputted through the output port in order to keep their original sequence.
FIG. 1 illustrates the circuit of such a prior art data cell re-sequencer, which is based on U.S. Ser. No. 005339311A entitled as xe2x80x9cData Packet Re-sequencer, filed by Jonathan S. Turner of Washington University. The circuit is designed to provide a time stamp by the common clock for representing the time of that a cell reaches the switch. In addition, the number of the slots to be selected by the selector of the buffer controller is limited by the number of the physical hardware which correspond to the number of AGE""s, namely xe2x80x9cBxe2x80x9d. This system does not provide such cell re-sequencing buffer as it may be required to cope with the various number of the data cell slots for meeting various traffic characteristics. Further, as the number of the data cell slots is increasedxe2x80x94for example, to meet an increase in Internet data trafficxe2x80x94the number of the control circuit should be increased also.
It is an object of the present invention to provide a cell re-sequencer for re-sequencing the ATM cells switched through the multiple paths so as to keep their original sequence in an ATM switching system, and a method thereof.
It is another object of the present invention to provide a cell re-sequencer for re-sequencing the ATM cells switched through the multiple paths based on the real delay that is the time difference between the input time of a data cell reaching the switching network of the ATM switching system and the output time of the cell leaving the switching network.
It is still another object of the present invention to provide a data cell re-sequencer for re-sequencing the ATM data cells switched through the multiple paths, which may provide a number of data cell slots to meet various traffic characteristics by initializing software.
According to an aspect of the present invention, a data cell re-sequencer for re-sequencing the data cells switched by an ATM switching system includes a maximum delay register for setting the maximum delay value by initializing for output the maximum delay value according to internal clock pulses, a base address increment register for incrementing the initial value of the initialization set as a base address one by one according to data cell time clock pulses, a delay detector for detecting the real delay of a data cell from its header, a data cell storing address generator for adding the base address to the delay difference between the maximum delay and real delay to generate a data cell storing address, a multiplexer for multiplexing the base address and data cell storing address according to the cell time clock pulses, and a memory address register for temporarily storing the output of the multiplexer.
The cell storing address generator can further comprise a subtractor for subtracting the real delay from the maximum delay to generate the delay difference, and an adder for adding the base address and delay difference.
The maximum delay value set by the maximum delay register can be determined by a maximum number of the slots for storing the cells switched by the ATM switching system.
The real delay can be the time difference between the input time of a cell reaching the switching network of the ATM switching system and the output time of the cell leaving the switching network.
The multiplexer may output the cell storing address at the rising edges of the cell time clock pulses and output the base address at the falling edges of the cell time clock pulses.
Another embodiment of a cell re-sequencer for re-sequencing the cells switched by an ATM switching system comprises:
a maximum delay register for setting a maximum delay value as an initial value by initializing an output of the maximum delay value according to internal clock pulses;
a base address increment register for increasing an initial value of an initialization set as a base address one by one according to cell time clock pulses;
a delay detector for detecting the real delay of a cell from its header;
a cell storing address generator for adding the base address to the delay difference between the maximum delay and real delay to generate a cell storing address;
a multiplexer for multiplexing the base address and cell-storing address according to the cell time clock pulses;
a memory address register for temporarily storing the output of the multiplexer;
a cell buffer for buffering said cells according to the internal clock pulses;
a memory buffer register for temporarily storing the cells from the cell buffer; and,
a cell buffer memory for storing the cells from the memory buffer register at the corresponding cell storing addresses provided from the memory address register to generate the cells according to the corresponding base addresses from the memory address register.
The above re-sequencer may further comprise a first flip-flop for latching the cell-receiving signal of the cell buffer representing the input of a cell;
a memory allocation map for storing the valid cell information of the cell at a cell storing address from the memory address register according to the cell receiving signal; and
a second flip-flop for latching the valid cell information.
The cell storing address generator may further includes a subtractor for subtracting the real delay from the maximum delay to generate the difference, and an adder for adding the base address and delay difference.
The maximum delay value set by the maximum delay register is determined by the maximum number of the slots for storing the cells switched by the ATM switching system.
The real delay can be the time difference between the input time of a cell reaching the switching network of the ATM switching system and the output time of the cell leaving the switching network.
The multiplexer may output the cell storing address at the rising edges of the cell time clock pulses and output the base address at the falling edges of the cell time clock pulses.
A first method of re-sequencing the cells switched by an ATM switching system, comprises the steps of:
(a) setting the maximum delay value by initializing an output of the maximum delay value according to internal clock pulses;
(b) increasing an initial value of an initialization set as a base address one by one according to cell time clock pulses;
(c) detecting the real delay of a cell from its header;
(d) adding the base address to the delay difference between the maximum delay and real delay to generate a cell storing address; and,
(e) multiplexing the base address and cell storing address according to the cell time clock pulses.
In a variation of the above method the address generation in step (d) further includes:
(1) subtracting the real delay from said maximum delay to generate the delay difference; and
(2) adding the base address and delay difference, wherein said maximum delay value in step (a) is determined by the maximum number of the slots for storing the cells switched by said ATM switching system.
In the above method, the real delay in step (c) may be equal to the time difference between the input time of a cell reaching the switching network of the ATM switching system and the output time of the cell leaving the switching network.
In the above method, the multiplexing in step (e) can comprise: (1) outputting the cell-storing address at the rising edges of the cell time clock pulses and (2) outputting the base address at the falling edges of the cell time clock pulses.
In a second method of re-sequencing the cells switched by an ATM switching system, comprises the steps of:
(a) setting the maximum delay value by initializing an output of the maximum delay value according to internal clock pulses;
(b) increasing an initial value of an initialization set as a base address one by one according to cell time clock pulses;
(c) detecting the real delay of a cell from its header;
(d) adding the base address to the delay difference between the maximum delay and real delay to generate a cell storing address;
(e) multiplexing the base address and cell storing address according to the cell time clock pulses;
(f) temporarily storing the base address and cell storing address;
(g) buffering the cells according to said internal clock pulses;
(h) temporarily storing the cells from the cell buffer; and,
(i) storing the cells at the corresponding cell storing addresses to generate the cells according to the corresponding base addresses.
The above second method can further including the steps of:
latching the cell-receiving signal representing the input of a cell;
(k) storing the valid cell information of the cell at a cell storing address according to the cell receiving signal; and,
(l) latching the valid cell information.
In the above second method, the address generation in step (d) can further include (1) subtracting the real delay from said maximum delay to generate said delay difference, and (2) adding the base address and delay difference.
In the above second method, the maximum delay value set in step (a) can be determined by the maximum number of the slots for storing the cells switched by the ATM switching system.
In the above second method, the real delay detected in step (c) can be equal to the time difference between the input time of a cell reaching the switching network of said ATM switching system and the output time of said cell leaving said switching network.
In the above second method, the multiplexing in step (e) includes (1) outputting the cell-storing address at the rising edges of the cell time clock pulses; and, (2) outputting the base address at the falling edges of the cell time clock pulses.
The present invention will now be described more specifically with reference to the attached drawings. Such drawings are presented for illustrative purposes of one embodiment of the invention and are not intended to limit the scope of the invention to the embodiment shown.